The fan-out wafer-level packaging (FOWLP) technology has been developed to produce semiconductors of reduced package sizes and pad layout flexibility. The FOWLP enables external terminals distributing outside of the chip by using a thin-film fan-out redistribution layer (RDL) at a wafer level format.
There are mainly two conventional fabrication technologies in the FOWLP field. First one is “Mold-first” method. The package produced by the “Mold-first” method faces challenges including (a) the package yield is dominated by the RDL yield, (b) the Input/Output (I/O) pitch of the chip embedded therein is limited by alignment mismatching between the chip and the RDL, and (c) the RDL requires a low-cure temperature resin which may negatively affect the package reliability.
To overcome these challenges, a “RDL-first” approach was developed. The “RDL-first” approach overcomes the challenges mentioned above for the “Mold-first” method, but such “RDL-first” approach still relies on polymer dielectric base Cu interconnections for the RDL. The minimum Line/Space (L/S) dimension is restricted as high as 2 um level.
To meet with higher I/O density, a 2.5D Silicon (Si) interposer solution was developed, and relevant products have been launched in the field programmable gate array (FPGA) market. The 2.5D Si interposer solution utilises 65 nm node Cu damascene interconnects as the “RDL”. The minimum L/S is 0.4 um, but there is enough room for scaling further.
FIG. 1 shows a schematic diagram of a semiconductor device 100 produced by the 2.5D packaging solution with Si interposer and Through Silicon Vias (TSVs). In the semiconductor device 100, stacked memories 20a-20d and a logic chip 30 are flip-chip bonded onto a Si interposer 10 with TSVs, which enables high density interconnection between logic and memory. However, the 2.5D Si interposer solution has a negative shortcoming: its high assembly cost. It requires TSV fabrication to achieve electrical connections between front 12 and back 13 sides of the Si interposer.
To achieve a high density interconnection like the Si interposer 100 without TSVs, a Silicon-less Interconnect Technology (SLIT) was developed. In the SLIT, the Si substrate is completely eliminated from the Si interposer, and backside interconnections can be done without any need for TSVs. Such structure would drastically reduce the fabrication cost of the TSV interposer as much as 40%.
However, in SLIT, the Si wafer is destroyed at the end of the process thereby increasing the cost of SLIT. The Si wafer cannot be recycled nor reused for any other purposes. Thus, there is large room to achieve SLIT cost reduction by utilizing Si wafer recycling and/or integrating devices into Si carriers.
Thus, what is needed is a FOWLP method that can exclude production of TSVs and can form devices integrated into the Si substrate/carrier. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.